The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 02, 2004

Filed:

Jun. 25, 2001
Applicant:
Inventors:

Nozomi Shimoishizaka, Kyoto, JP;

Ryuichi Sahara, Hirakata, JP;

Yoshifumi Nakamura, Neyagawa, JP;

Takahiro Kumakawa, Takatsuki, JP;

Shinji Murakami, Yawata, JP;

Yutaka Harada, Kyoto, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/348 ;
U.S. Cl.
CPC ...
H01L 2/348 ;
Abstract

A low elasticity layer ( ) having an opening in an electrode arranging area where element electrodes are disposed is provided on a main surface of a semiconductor substrate ( ). On the low elasticity layer ( ), lands ( ) serving as external electrodes are disposed, and pads ( ) on the element electrodes, the lands ( ) and metal wires ( ) for connecting them are integrally formed as a metal wiring pattern ( ). A solder resist film ( ) having an opening for exposing a part of each land ( ) is formed, and a metal ball ( ) is provided on the land ( ) in the opening. The low elasticity layer ( ) absorbs thermal stress and the like caused in heating or cooling the semiconductor device, so as to prevent disconnection of the metal wires ( ).


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