The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 02, 2004
Filed:
Dec. 14, 2001
Semiconductor devices having a non-volatile memory transistor and methods for manufacturing the same
Applicant:
Inventor:
Tomoyuki Furuhata, Sakata, JP;
Assignee:
Seiko Epson Corporation, Tokyo, JP;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/976 ; H01L 2/994 ; H01L 3/1062 ; H01L 3/1113 ; H01L 3/1119 ; H01L 2/9788 ; H01L 2/9792 ;
U.S. Cl.
CPC ...
H01L 2/976 ; H01L 2/994 ; H01L 3/1062 ; H01L 3/1113 ; H01L 3/1119 ; H01L 2/9788 ; H01L 2/9792 ;
Abstract
Semiconductor devices including a non-volatile memory transistor and methods for manufacturing such semiconductor devices are described. One semiconductor device may include a silicon substrate , a floating gate disposed above the silicon substrate through a first dielectric layer , a second dielectric layer that contacts at least a part of the floating gate , a control gate formed over the second dielectric layer , and a source region and a drain region formed in the silicon substrate . A wiring layer is provided above the floating gate , and the entirety of the floating gate is overlapped by the wiring layer as viewed in a plan view.