The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6812165 B1

PDF
Full Text
Expired
Date of Patent:
Nov. 02, 2004

Filed:

Aug. 19, 2003
Applicant:
Inventors:

Hidenori Sato, Ome, JP;

Yoshiyuki Hayashi, Hino, JP;

Toshio Ando, Kunitachi, JP;

Assignee:

Other;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/131 ; H01L 2/1469 ;
U.S. Cl.
CPC ...
H01L 2/131 ; H01L 2/1469 ;
Abstract

Described is a manufacturing method of a semiconductor integrated circuit device by depositing a silicon nitride film to give a uniform thickness over the main surface of a semiconductor wafer having a high pattern density region and a low pattern density region. This is attained by, upon depositing a silicon nitride film over a substrate having a high gate-electrode-pattern density region and a low gate-electrode-pattern density region by using a single-wafer cold-wall thermal CVD reactor, setting a flow rate ratio of ammonia (NH ) to monosilane (SiH ) greater than that upon deposition of a silicon nitride film over a flat substrate.


Find Patent Forward Citations

Sato, Hidenori. (2004). Manufacturing method of semiconductor integrated circuit device (U.S. Patent No. 6812165). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6812165

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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