The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 26, 2004

Filed:

May. 16, 2003
Applicant:
Inventors:

Kenji Toyoda, Osaka, JP;

Michihito Ueda, Takatsuki, JP;

Kiyoshi Morimoto, Hirakata, JP;

Kiyoyuki Morita, Yawata, JP;

Toru Iwata, Osaka, JP;

Jun Kajiwara, Yawata, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 1/122 ; G11C 1/124 ;
U.S. Cl.
CPC ...
G11C 1/122 ; G11C 1/124 ;
Abstract

A potential generating circuit comprises a capacitor ( ); a ferroelectric capacitor ( ) connected in series to the capacitor ( ); an output terminal ( ); a capacitor ( ) for grounding the output terminal ( ); a switch ( ) for connecting a connecting node ( ) between the two capacitors ( ) to the output terminal ( ); and a switch ( ) for connecting the connecting node ( ) to the ground; wherein during a first period, with the switches ( ) and ( ) placed in the OFF state, a terminal ( ) is provided with a positive potential and a terminal ( ) is grounded; wherein during a second period following the first period, the terminal ( ) is grounded and the switch ( ) is placed in the ON state; wherein during a third period following the second period, the switch ( ) is placed in the OFF state, the switch ( ) is placed in the ON state, and the terminal ( ) is provided with a positive potential; wherein during a fourth period following the third period, the terminal ( ) is grounded; and wherein the first through fourth periods are repeated.


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