The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 26, 2004

Filed:

May. 12, 2003
Applicant:
Inventors:

Kae Wong, Dallas, TX (US);

Xiaoyu Xi, Plano, TX (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03F 3/26 ;
U.S. Cl.
CPC ...
H03F 3/26 ;
Abstract

An output stage provides increased current sourcing capability through a technique of local positive feedback. Current through a transistor MP is mirrored by the output current source I that is desired to be increased. Without positive feedback, the gate of MN would be fixed by MP and MN , and when input voltage V decreases by an incremental voltage &Dgr;V, the resulting current increase would distribute an increased voltage not only across MP 's V but also in the V of another transistor MN ; therefore, undesirably, not all of the &Dgr;V voltage change is mirrored in I . However, if positive feedback such as MP is provided, the feedback dynamically increases the voltage at the gate of MN . The increased voltage of MN 's gate essentially provides more voltage “headroom” for MP and MN , and allows current through MP to increase with any voltage decrease in V . Through current mirroring, the increased current through MP ultimately results in the desired higher maximum output current source I . This increase in output current sourcing is achieved with a minimal additional circuitry—a single transistor, MP . The feedback is local (internal to the output stage), so that loop delay is minimal and response is fast. Further, because of improved DC gain within the output stage, the increased maximum I is achieved without compromising other circuit parameters such as power supply rejection ratio (PSRR).


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