Ddr-ii driver impedance adjustment control algorithm and interface circuits

Abstract

A memory interface device uses a driver impedance adjustment engine with state machine for off chip driver (OCD) calibration which is used to set the driver voltage levels of the DRAM memory module or DIMM of the JEDEC DDR-II standard type. By adjusting the pull-up drive strength and pull-down drive strength, the output voltage levels and the rise times can be optimized to find the minimal signal swing that is still immune to noise, while not degrading the data eye significantly. The state machine finds the optimal setting for the DRAM Driver Impedance, using both DC and AC methods adjusting the value of the driver impedance through a master ASIC, and then sampling the known value sent back from the DRAM. The state machine will stop when the optimal value of the driver impedance is found and automates the process of detecting the optimal driver impedance and configuring the DRAM module or DIMM accordingly. The ASIC circuit and method use a data strobe, not only as strobe, but as data input during OCD calibration. Optimal driver impedance setting of a DDR-II DRAM is detected in a DC mode. Using AC-BIST the optimal driver impedance setting can be adjusted and optimized to account for AC timing influences such as coupled noise, data dependent jitter, and intersymbol interference.