The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 19, 2004
Filed:
Jul. 16, 2002
Applicant:
Inventor:
Amit Kumar Premy, Guna, IN;
Assignee:
Texas Instruments Incorporated, Dallas, TX (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/900 ;
U.S. Cl.
CPC ...
G06F 1/900 ;
Abstract
A method of measuring the PLL lock time includes deriving the PLL frequency-settling function by demodulation and envelope extraction in the time domain. The PLL lock time can then be calculated from this function. Using this PLL lock time measurement method provides for very good frequency and time accuracy. Also, since for demodulation, the settled signal is used for multiplication, ATE synchronization is not required. Furthermore, since all the processing is done in the time domain, calculation times are reduced, making the process suitable for ATE environments.