Interconnect structure for an integrated circuit and corresponding fabrication method

Abstract

The present invention relates to an interconnect structure for an integrated circuit ( ) having a first interconnect (B ; B ′; B ″), which is composed of a plurality of interconnect sections (A -A ; A ′-A ′; A ″-A ″) lying in a first and a second interconnect plane (M , M ); and a second interconnect (B ; B ′; B ″), which runs adjacent to the first interconnect (B ; B ′; B ″) and which is composed of a plurality of interconnect sections (A -A ; A ′-A ′; A ″-A ″) lying in the first and second interconnect planes (M , M ); the first and second interconnects (B ; B ′; B ″; B ; B ′; B ″) being offset with respect to one another in the longitudinal direction in such a way that the interconnect sections (A , A , A ; A ′, A ′, A ′; A ″, A ″) of the first interconnect (B ; B ′; B ″) which lie in the first interconnect plane (M ) run at least in sections beside the interconnect sections (A , A ; A ′; A ′; A ″, A ″) of the second interconnect (B ; B ′; B ″) which lie in the second interconnection plane (M ), and that the interconnect sections (A , A , A ; A ′, A ′, A ′; A ″, A ″) of the first interconnect (B ; B ′; B ″) which lie in the second interconnect plane (M ) run at least in sections beside the interconnect sections (A , A , A ; A ′, A ′, A ′; A ″) of the second interconnect (B ; B ′; B ″) which lie in the first interconnect plane (M ). The invention also provides a corresponding fabrication method.