The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 19, 2004

Filed:

Mar. 20, 2001
Applicant:
Inventors:

Larry Leighton, Scottsdale, AZ (US);

Prasanth Perugupalli, Tempe, AZ (US);

Nagaraj Dixit, Gilbert, AZ (US);

Tom Moller, Gilroy, CA (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/166 ; H01L 2/100 ; G01R 3/126 ;
U.S. Cl.
CPC ...
H01L 2/166 ; H01L 2/100 ; G01R 3/126 ;
Abstract

A method for manufacturing a power transistor circuit includes securing a die to a substrate, the die comprising a transistor having an input terminal and an output terminal. One or more performance characteristics of the transistor are measured. Using one or more wire sets, the transistor input terminal is electrically connected to one or more input matching elements and an input signal lead. The impedance of the one or more wire sets, as determined by selecting a desired number and/or length of the wires in each set, is selected based at least in part on the measured transistor performance characteristic(s). Similarly, using one or more additional wire sets, the transistor output terminal is electrically connected to one or more output matching elements and an output signal lead, wherein the impedance of the additional wire sets is selected based at least in part on the measured transistor performance characteristic(s).


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