System and method for using a network timing reference circuit as a phase detector in a synchronization loop

Abstract

An improvement to system clock synchronization corrector in a digital transceiver allows the generation of a phase error correction signal for use in an imbedded clock synchronization control loop without the use of additional transmitted information or additional external circuitry. The system allows a transceiver to achieve timing and synchronization lock to a system master clock, such as a T1 or E1 clock, by triggering a counter to supply a count responsive to a higher-frequency replica of the local clock signal with the network clock signal. A network timing reference unit generates a phase error offset by clocking data into comparison registers in response to the maximum counter values. Subsequent counter values are mathematically combined to generate a series of phase offset samples. The phase error samples may be stored and or further manipulated to generate a phase error correction signal for use in a clock synchronization control loop. The network timing reference unit may comprise a counter, an input register, a first comparison register, a second comparison register, and an adder. The present invention provides a method for generating a phase offset. In its broadest terms, the method can be described as: receiving a network clock and a local clock; using a higher-frequency replica of the local clock to generate a counter input signal; recording counter output values at intervals responsive to the network clock; comparing subsequent counter values at intervals responsive to a maximum value of the counter; and combining subsequent counter values to generate a series of phase error samples.