The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 12, 2004
Filed:
Feb. 26, 2003
Peter Schrögmeier, München, DE;
Stefan Dietrich, Turkenfeld, DE;
Sabine Kieser, Hausham, DE;
Pramod Acharya, Munich, DE;
Infineon Technologies AG, Munich, DE;
Abstract
Latency time circuit for an S-DRAM ( ), which is clocked by a high-frequency clock signal (CLK), for producing a delayed data enable signal for synchronous data transfer through a data path ( ) of the S-DRAM ( ), having a controllable latency time generator ( ) for delaying a decoded external data enable signal (PAR) with an adjustable latency time, which a comparison circuit ( ) which compares a cycle time (t ) of the high-frequency clock signal (CLK) with a predetermined signal delay time of the data path ( ), and reduces the latency time of the latency time generator ( ) by the cycle time if the signal delay time of the data path ( ) is greater than the cycle time (t ) of the clock signal (CLK)