The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 12, 2004
Filed:
Feb. 01, 2002
Applicant:
Inventor:
Atsuki Inoue, Kawasaki, JP;
Assignee:
Fujitsu Limited, Kawasaki, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 1/9096 ;
U.S. Cl.
CPC ...
H03K 1/9096 ;
Abstract
A circuit arrangement uses differential pass transistor logic, a low voltage swing and charge recycling to save power, in which the swing voltage is reduced, but the supply voltage is not reduced, thereby maintaining the transistor device current and avoiding speed degradation. SOI devices including an adder, which uses this circuit arrangement, can avoid the body effect to long pass transistor network and improve the speed at lower supply voltage.
Quick Actions:
Inoue, Atsuki. (2004). Reduced swing charge recycling circuit arrangement and adder including the same (U.S. Patent No. 6803793). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6803793
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile