The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 05, 2004
Filed:
Jul. 16, 2002
Katsuya Arai, Kyoto, JP;
Toshihiro Kohgami, Kyoto, JP;
Matsushita Electric Industrial Co., Ltd., Osaka, JP;
Abstract
A semiconductor integrated circuit device includes an external connection pad, an electrostatic discharge protection circuit, an output circuit, an output pre-buffer circuit and an internal circuit, and is configured so that the output circuit is protected by the electrostatic discharge protection circuit from a surge entering through the external connection pad. A substrate-potential-fixing PMIS transistor whose gate is connected to the external connection pad is provided between an n-type substrate region (n well) and a power supply line. When a positive charge is applied to the external connection pad in an ESD test, the substrate-potential-fixing PMIS transistor is turned OFF, thereby suppressing an increase in the potential of the power supply line and suppressing a decrease in the surge withstand voltage of the output circuit.