The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6801080 B1

PDF
Full Text
Expired
Date of Patent:
Oct. 05, 2004

Filed:

Apr. 07, 2003
Applicant:
Inventor:

Christopher G. Arcus, San Jose, CA (US);

Assignee:

Pericom Semiconductor Corp., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06G 7/26 ;
U.S. Cl.
CPC ...
G06G 7/26 ;
Abstract

A differential input buffer shows reduced sensitivity to input conditions such as input-trace loading and upstream driver characteristics. Varying input conditions can be measured as differences in amplitude, slew rate, and common-mode offset. Wide input-voltage swings are clamped to a limited voltage range by an input clamp circuit that uses source followers to drive p-channel clamp transistors that turn off when the input voltage is too low. A voltage divider then sets the lowest voltage input to a differential stage. The differential stage receives the clamped inputs and has two tail current sinks to reduce delay sensitivity to charging and discharging of tail capacitances. A middle voltage is applied to transistors opposite the differential transistors that receive the clamped input voltages. A bias voltage for the tail current sinks is generated by mirroring currents and setting a gate voltage by injecting and removing a same bias current from a resistor.


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