The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 05, 2004
Filed:
May. 04, 1998
Robert R. Livolsi, Shokan, NY (US);
Juergen Pille, Stuttgart, DE;
International Business Machines Corporation, Armonk, NY (US);
Abstract
A receiving latch with hysteresis circuit for receiving data on cross chip boundaries in a chip to chip interface has a clock section and a feed section and a hysteresis latch section with the feed section receiver enable input pin for a dataline passing through the receiver feed section and hysteresis latch section. The receiver enable input pin D is settable to a high or low voltage level, respectively turning the hysteresis latch section on said dataline ON or OFF. The hysteresis latch pass gate has clock couplings to the pgate and ngate of the PFET and NFET transistors of the pass gate. The drains of said pass gate PFET and NFET are coupled to ground and their sources to a positive potential provided over said data line. The drain of a latch PFET has its source connected to a positive potential and the source of an latch NFET has having its drain connected to ground and both the latch PFET and NFET have their gate connection to the dataline latch output for gating the dataline information out of the latch from the latch gates of the hysteresis latch section.