The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 05, 2004
Filed:
Oct. 11, 2002
Applicant:
Inventors:
Daniel J. Pugh, San Jose, CA (US);
Andrew W. Fox, Pacific Grove, CA (US);
Dale Wong, San Francisco, CA (US);
Assignee:
Leopard Logic, Inc., Cupertino, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/500 ;
U.S. Cl.
CPC ...
H01L 2/500 ;
Abstract
A Field Programmable Gate Array (FPGA) core cell with one or more Look-Up Tables (LUTs) and a selectable logic gate is presented as a space-efficient alternative to the conventional LUT-based FPGA core cell. An algorithm based upon the familiar FlowMap algorithm for LUT-based FPGA core cells implements the mapping of a Boolean logic network into the disclosed FPGA core cell.
Pugh, Daniel. (2004). Field programmable gate array core cell with efficient logic packing (U.S. Patent No. 6801052). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6801052
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile