The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 05, 2004

Filed:

Dec. 10, 1999
Applicant:
Inventor:

Tomoyuki Furuhata, Sakata, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/9788 ;
U.S. Cl.
CPC ...
H01L 2/9788 ;
Abstract

Certain embodiments include a semiconductor device capable of preventing a retardation of signal transmission between the smallest units, a method for the manufacture thereof, a circuit substrate and an electronic device. Embodiments also include a manufacturing method comprising a laminating step of forming tunnel insulating films and , floating gates and , dielectric films and , control gates and on first and second memory cell areas and formed mutually adjacent to each other on a semiconductor substrate , a plurality of impurity area formation steps of forming sources and drains and on the first and second memory cell areas and , and forming a connecting area capable of forming an electric connection between one of the source and drain of the first memory cell area and one of the source and drain of the second memory cell area . The connecting area is formed to have a lower electric resistance than impurity areas and formed in one of the of impurity area formation steps.


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