The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 28, 2004
Filed:
Dec. 23, 2002
Applicant:
Inventor:
Tetsuo Miyamoto, Kawasaki, JP;
Assignee:
Fujitsu Limited, Kawasaki, JP;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/750 ;
U.S. Cl.
CPC ...
G06F 1/750 ;
Abstract
An integrated circuit layout method for placing a plurality of cells within a chip comprises a process for sorting the plurality of cells (or function macros) that are to be laid out in order of their delay times (or operation speed margins for macro), placing cells (or macros) having the largest delay times (or smallest speed margin for macro) closer to the peripheral area of the chip, and as the cell delay times get smaller(or the speed margins get larger), placing the relevant cells (or macros) closer to the central area of the chip.