The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 28, 2004
Filed:
Dec. 19, 2002
Eileen H. You, Saratoga, CA (US);
Matthew E. Becker, Harvard, MA (US);
Thomas E. Dillinger, Chelmsford, MA (US);
Micah C. Knapp, Cambridge, MA (US);
Daniel J. Flees, San Jose, CA (US);
Peter R. O'Brien, Austin, TX (US);
Chung Lau Chan, San Carlos, CA (US);
Sun Microsystems, Inc., Palo Alto, CA (US);
Abstract
In accordance with the present invention, a method, system, computer system, and computer program product for considering clock skew in designing digital systems with latch-controlled circuits are provided. The disclosure teaches a method for determining whether logic operations can be performed within the available time and allows detailed modeling of clock skew for different domains of the integrated circuit. Taking clock skew into account for each domain, worst-case timing paths can be determined for circuits controlled by either flip-flops or latches. A design of an integrated circuit can be revised or verified using the method taught. The disclosure envisions that integrated circuits, printed circuit boards, computer systems and other components will be manufactured based upon designs developed with the method taught.