The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 28, 2004

Filed:

Nov. 13, 2000
Applicant:
Inventor:

Koichi Hatta, Kawasaki, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04B 1/700 ; H04B 3/46 ; H04Q 1/20 ;
U.S. Cl.
CPC ...
H04B 1/700 ; H04B 3/46 ; H04Q 1/20 ;
Abstract

A testing system is provided with a pseudo random number generating circuit which generates a pseudo random number on the basis of a 125 MHz clock output from a 5-multiply circuit inside a clock recovery circuit, and an expected value generating/comparator circuit which collates a 125 Mbps recovered data output from the clock recovery circuit with an expected value data each 5 bits, and outputs the collation result as a 1-bit test output. The clock recovery circuit and the testing system are provided on the same LSI and are operated at a 125 MHz high frequency clock. However, the clock recovery circuit outputs a test output as recognized as a 25 MHz low speed data in the outside of LSI to the external elements.


Find Patent Forward Citations

Hatta, Koichi. (2004). Testing system (U.S. Patent No. 6798831). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6798831

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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