The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 28, 2004
Filed:
May. 27, 2003
Christian Ebner, Munich, DE;
Xignal Technologies AG, Unterhaching, DE;
Abstract
An integrated circuit arrangement is provided according to the present invention, including a cascoded current source ( ) and an adjusting circuit ( ) for adjusting the operating point (Vg1, Vg2, Vx) of the cascoded current source ( ) by providing gate potentials (Vg1, Vg2) for current source FETs (Q , Q ), the adjusting circuit having: a reference stage, formed by a pair of reference FETs (M , M ), which are supplied with reference currents (Iref1, Iref2) in such a way that the current densities in the reference FETs (M , M ) differ by a predetermined factor (N ), for providing reference gate potentials (Vgs1, Vgs2) at the gates of the reference FETs (M , M ); a processing stage, for providing an adjustment potential (Vgt1+V1) on the basis of the predetermined factor (N ), which is equal to the effective control voltage (Vgt1) of the first reference FET (M ) plus a predetermined additional voltage (V1), and an output FET (M ), which is connected on the source side to the adjustment potential (Vgt1+V1). Therefore, the present invention provides a circuit for operating point adjustment of a cascoded FET current source, independent of process and temperature variations, which may be used in many highly integrated analog circuits and maximizes the dynamic range.