Physical linearity test for integrated circuit delay lines

Abstract

A method and apparatus are provided for testing linearity of two or more programmable delay chains in an integrated circuit. A first delay chain is successively programmed to a first sequence of delay settings and, for each delay setting in the first sequence, a second delay chain is successively programmed to a second sequence of delay settings. The second sequence sweeps a propagation delay through the second delay chain from a delay value less than a present propagation delay through the first delay chain to a delay value greater than the present propagation delay. For each delay setting of the second delay chain, a logic transition is applied to inputs of the first and second delay chains and the output of one of the first and second delay chains is latched as a function of the output of the other of the first and second delay chains to produce a sample value. The sample values produced for each delay setting in the first sequence are monitored to determining whether the logic transition occurs in the sample values within an expected time window.