The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 28, 2004

Filed:

Apr. 30, 2002
Applicant:
Inventors:

Erik Jan Lous, Nijmegen, NL;

Albertus Theodorus Maria Van De Goor, Nijmegen, NL;

Anco Heringa, Eindhoven, NL;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/144 ;
U.S. Cl.
CPC ...
H01L 2/144 ;
Abstract

A method of manufacturing a semiconductor device, in which a surface ( ) of a semiconductor body ( ) is provided with a first metallization layer comprising conductor tracks ( ), among which a number having a width w an a number having a greater width. On this structure an insulating layer ( ) is deposited by means of a process in which the thickness of the formed insulating layer ( ) is dependent on the width of the subjacent conductor tracks ( ), after which a capping layer ( ) is deposited on the insulating layer ( ). Then the silicon oxide layer is planarized by means of a polishing process. In this method, the conductor tracks having a width greater than w are split up into a number of parallel strips ( ) having a width w, which strips are locally connected to one another.


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Lous, Erik. (2004). Method of manufacturing a semiconductor device (U.S. Patent No. 6797615). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6797615

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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