Memory access controller with response faking

Abstract

A memory controller controls access to one or more memory units. The memory controller includes access control logic operable to receive a memory access request that references at least one memory address. It further includes a fake response record operable to record a fake response indication for an address for which a response is to be faked. The access control logic is operable on receipt of a memory access request to access the fake response record and to fake a response where a fake response indication for an address indicates that a response is to be faked. By providing such a faked response, an embodiment of the invention is able avoid multiple exceptions for the same memory location in a CPU. Also, by providing such a faked response, multiple bus errors for a memory location can also be avoided where a bus supports Direct Memory Access (DMA). The memory controller can be implemented in an integrated circuit. It can form part of a memory subsystem including the memory controller and at least one memory unit in an integrated circuit.