Bus bridge resource access controller

Abstract

Resource access control is provided in a manner that avoids unnecessary resource accesses where a resource is already known to be faulty. A resource access controller controls access to resources addressed by at least one central processing unit. The resource access controller includes an address translation mechanism providing fake response identification as to whether or not a response is to be faked. The resource access controller also includes a fake response generator for selectively generating a faked response where the fake response identification of the corresponding translation entry indicates that a response is to be faked. The resource access controller is able to associate fake response indications with a resource and to generate a fake response when an attempt is made to access a resource labeled such that a faked response should be returned. The resource access controller can form part of a bridge that interconnects a first bus connected to a processor of the computer system, which processor includes at least one said central processing unit, and at least a second bus. However, the resource access controller can be provided at other points in a computer system where an address translation is performed, for example in a memory management unit.