The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 21, 2004
Filed:
Apr. 11, 2000
Christopher G. Riedle, Apex, NC (US);
Jean-Claude Abbiate, La Gaude, FR;
Alain Richard Blanc, Tourrettes sur Loop, FR;
Daniel Wind, Drap, FR;
International Business Machines Corporation, Armonk, NY (US);
Abstract
An apparatus and process for updating a sample time in a serial link which converts serial data in parallel data. A delay line stores multiple samples of at least two data bits received over the serial link. The contents of the delay line are matched so that they can be analyzed by a processor to determine an optimum sampling position in the delay line. The processor is programmed to analyze contents of the latch by creating a sample mask from a plurality of delay line samples. The sample mask identifies transition edges of first and second data bits within the delay line. The transition edges are validated with respect to the presence, for first and second initial sampling positions for the respective data bits. New sampling positions are determined from the validated edges, and the initial sampling positions are updated with sampling positions which have been determined from the new sampling positions. In this way phase jitter induced by environmental concerns is minimized using new sampling positions along the delay line for coding the data into parallel data.