The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 21, 2004

Filed:

Apr. 23, 1998
Applicant:
Inventors:

Shawn A. Clayton, Boylston, MA (US);

David R. Follett, Boxborough, MA (US);

Nitin D. Godiwala, Boylston, MA (US);

Maria C. Gutierrez, Concord, MA (US);

David S. Wells, Bolton, MA (US);

James B. Williams, Lowell, MA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 1/228 ;
U.S. Cl.
CPC ...
H04L 1/228 ;
Abstract

A system includes interconnected computers and switching nodes. A source computer for the virtual circuits schedules message transmissions on a round-robin basis. Each switching node also forwards messages in a round-robin manner, and a destination computer schedules processing of received messages in a round-robin manner. In addition, messages are transmitted in cells to reduce delays in short messages if long messages are transmitted for one virtual circuit before transmission of a short message for another virtual circuit. For each virtual circuit, the destination computer and each switching node can generate a virtual circuit flow control message to temporarily limit transmissions if the resources being taken up by messages exceed predetermined thresholds. In addition, each switching node or computer can generate link flow control messages for transmission to neighboring devices to temporarily limit transmissions if the resources taken up by all virtual circuits exceeds predetermined thresholds.


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