The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 21, 2004
Filed:
Sep. 04, 2002
Hyun Lee, Ladera Ranch, CA (US);
Trevor Edward Little, Allentown, PA (US);
Agere Systems Inc., Allentown, PA (US);
Abstract
Multiple level logic bus drivers and receivers communicate over a bus using a multiple-level logic protocol that transfers multiple bits on each signal wire of a bus in a given interval without increasing the bus width or power dissipation. In one embodiment, four logic levels are employed using CMOS transistor circuitry operating with low voltage (e.g., 1.2V or 1.3V) power supplies (V ) and P and N transistor threshold voltage levels of V and V on the order of 0.4--0.5V. Thus, the separation between the following four logic levels is approximately uniform: V ; V −V ; V +V ; and V . The approximately equal voltage gaps between each quantization level provide uniform noise margins for all levels. A bus noise minimization scheme and a quick recovery scheme ensure the correct data transfer in the presence of injected noise. An initial over drive feature is disclosed for shorter transition times.