Field effect transistor with reverse dopant grandient region

Abstract

A p -type impurity layer is provided at a position located below n -type impurity layers which are to become the drain of a MOSFET. Although the p -type impurity layer is of the same conductivity type as a semiconductor substrate, the p -type impurity layer is lower in doping level than the semiconductor substrate. The p -type impurity layer is formed so as to be joined to an n -type impurity layer and such that the dosage of p-type impurity (i.e., the amount of included impurity) becomes higher with increasing distance from the thus-formed junction. The dosage of the area located in the vicinity of the junction is made lower, thereby rendering a depletion layer easy to spread when a drain voltage is applied. Thus, capacitance Cds developing between the drain and the substrate is reduced, and the operating speed of the MOSFET increases. Further, the structure of the MOSFET reduces fluctuations in the capacitance Cds stemming from fluctuations in the drain voltage, thereby suppressing power leakage and improving output efficiency.