The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 07, 2004

Filed:

Apr. 07, 2002
Applicant:
Inventors:

Sunderarjan Mohan, Mountain View, CA (US);

Xiling Shen, Stanford, CA (US);

Assignee:

Barcelona Design, Inc., Newark, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/750 ;
U.S. Cl.
CPC ...
G06F 1/750 ;
Abstract

A method is described that involves retrieving a generic layout description of a circuit structure from a first database that stores a plurality of generic layout descriptions. The method also involves retrieving a foundry design rule profile of a semiconductor manufacturing process from a second database that stores a plurality of semiconductor manufacturing process design rule profiles. The method also involves automatically generating a layout of the circuit structure that conforms to the foundry design rule


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Mohan, Sunderarjan. (2004). Method and apparatus for automatic layout of circuit structures (U.S. Patent No. 6789246). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6789246

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