Arrangement and method of testing an integrated circuit

Abstract

In an arrangement for testing an integrated circuit comprising at least two circuit sections ( ) which in normal operation operate with at least two different clock signals, a minimal number of test runs for testing the integrated circuit is required because the integrated circuit to be tested is formed in such a way that each clock signal can be individually switched on and off during a test by test software provided in the arrangement, a software model of the circuit to be tested is provided in the arrangement, which software model comprises an X generator ( ) for those circuit components ( ) whose mode of operation is influenced by a plurality of clock signals and their skew behavior, which X generator is activated and supplies an X signal when more than one clock signal influencing the mode of operation of the circuit components ( ) during testing is activated, while, during testing, the test software initially activates all clock signals and evaluates test results for those circuit components ( ) for which no X signal appears in the software model ( ), and because for those circuit components ( ) for which an X signal appeared in the software model ( ) during testing with all clock signals, the test software performs a plurality of test runs in which each time only one or more of the clock signals influencing the mode of operation of the circuit component ( ) is/are activated and evaluates only those tests of the circuit components ( ) of the circuit for which no X signal appears in the software model ( ).