The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 07, 2004
Filed:
Jan. 08, 2003
Applicant:
Inventor:
Aninda K. Roy, San Jose, CA (US);
Assignee:
n Microsystems, Inc., Santa Clara, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 3/12 ;
U.S. Cl.
CPC ...
H03K 3/12 ;
Abstract
A method and apparatus for delaying a clock signal involves a first clock path arranged to propagate a first clock signal; a second clock path arranged to propagate a second clock signal; and an interpolator arranged as a unity gain operational amplifier. An amount of delay between the first and second clock signals is determined by a control voltage potential.
Roy, Aninda. (2004). Unity gain interpolator for delay locked loops (U.S. Patent No. 6788123). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6788123
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile