The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 07, 2004
Filed:
Mar. 28, 2003
Mei-Hua Chung, San Jose, CA (US);
Ching-Hwa Chen, Milpitas, CA (US);
Vei-Han Chan, San Jose, CA (US);
Mosel Vitelic, Inc., Hsin-Chu, TW;
Abstract
Nonvolatile memory wordlines ( ) are formed as sidewall spacers on sidewalls of row structures ( ). Each row structure may contain floating and control gates ( ), or some other elements. Pedestals ( ) are formed adjacent to the row structures before the conductive layer ( ) for the wordlines is deposited. The pedestals are formed in the area of the contact openings ( ) that will be etched in an overlying dielectric ( ) to form contacts to the wordlines. The pedestals raise the top surface of the wordline layer near the contact openings, so the contact opening etch can be made shorter. The pedestals also increase the minimum thickness of the wordline layer near the contact openings, so the loss of the wordline layer during the etch of the contact openings becomes less critical, and the photolithographic tolerances required for patterning the contact openings can be relaxed. The pedestals can be dummy structures (they may have no electrical functionality).