The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 31, 2004

Filed:

Jun. 27, 2000
Applicant:
Inventor:

Atsuko Kozai, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/750 ;
U.S. Cl.
CPC ...
G06F 1/750 ;
Abstract

In a placement and routing for a standard cell type LSI design, each standard cell comprises a VDD power supply terminal formed of a P-type diffused layer, a VSS power supply terminal formed of an N-type diffused layer, and an input terminal and an output terminal formed of a first level metal. A plurality of standard cells are located to form a standard cell array, and VDD and VSS power supply lines formed of the first level metal are located to extend along opposite sides of the standard cell array, respectively. For connecting the power supply terminal of the standard cell to the power supply line of the first level metal, a power supply line formed of the diffused layer is extended from the power supply terminal to the power supply line of the first level metal, and a contact bole is formed at an overlapping portion between the power supply line of the first level metal and power supply line formed of the diffused layer. Thus, it is possible to place and route standard cells having different widths with no hindrance, and it is also possible to form an inter-cell connection in the device formation region between the power supply line and the wiring area within the cell. In addition, it is possible to set the width of the power supply line of the first level metal to an appropriate width for each standard cell array.


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