Error-correcting code adapted for memories that store multiple bits per storage cell

Abstract

A memory that stores a plurality of data storage words, each data storage word includes a plurality of data storage cells arranged as a plurality of columns of data storage cells, at least one of the data storage cells storing data specifying a data value having 3 or more states. The memory includes a plurality of data lines, one such data line corresponding to each column of data storage cells. Each data storage cell sets its state or provides a signal representative of its state via the data line connected to that cell in response to control signals. The memory also includes an error encryption circuit for receiving a data word to be stored in the memory and generating therefrom an encrypted data storage word. The encryption circuit divides the encrypted data storage word into a plurality of sub-data storage words. The two least significant bits of the sub-data storage words are encrypted via a first error-encryption algorithm and the most significant bits of the sub-data storage words are either not encrypted or encrypted via a second error encryption algorithm, the second error encryption algorithm having a Hamming Distance that is less than the Hamming Distance of the first error-encryption algorithm. An error decrypting circuit generates a corrected data word from the uncorrected sub-data storage words by generating an increment or decrement to be added to an uncorrected sub-data storage word to arrive at a correct sub-data storage word value.