The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 31, 2004
Filed:
Dec. 23, 2002
Yoshiki Kobayashi, Tokyo, JP;
Oki Electric Industry Co., Ltd., Tokyo, JP;
Abstract
In a semiconductor memory device according to the present invention, which allows a memory cell array unit and a memory circuit internal logic unit to be tested independently of each other, a first test circuit unit TCi to which an address signal a″, a scan-in signal SIN, a scan select signal SS and a shift clock signal SCLK are input, outputs an address signal a′″ and a scan-out signal SiOUT The address signal a′″ is input to the memory cell array unit MCA and a column selector CS, whereas the scan-out signal SiOUT is input to a second test circuit unit TCi The second test circuit unit TCi to which the scan-out signal SiOUT the scan select signal SS, a write control signal WCTRL and a scan clock signal SCLK are input, outputs at a scan-out signal SOUT. The first test circuit unit and the second test circuit unit each achieve a parallel/serial conversion function.