The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 31, 2004
Filed:
Sep. 28, 2000
Hiroaki Kudo, Nara, JP;
Sharp Kabushiki Kaisha, Osaka, JP;
Abstract
An amplification type solid state imaging device of the present invention includes a plurality of pixels arranged in a matrix each of which includes: a photodiode for photoelectric conversion; a signal amplification MOS transistor which functions as an amplifier for amplifying a change in the potential of the photodiode; a pixel selection MOS transistor; and a reset MOS transistor for resetting the potential of the photodiode to a predetermined initial potential, gate terminals of the selection MOS transistors of the pixels along each row being commonly connected together with a predetermined signal read pulse being applied to the gate terminals, gate terminals of the reset MOS transistors of the pixels along each row being commonly connected together with a predetermined reset pulse being applied to the gate terminals, and terminals on one end of the selection MOS transistors of the pixels along each column being commonly connected together to form a signal line, wherein a shutter reset operation is performed by applying a shutter operation reset pulse to the gate terminals of the reset MOS transistors during a period which is different from a period during which the reset pulse is applied to the gate terminals of the reset MOS transistors in a pixel signal read operation. The shutter operation reset pulse is applied to the gate terminals of the reset MOS transistors in a state where a potential of the signal line is set to a predetermined fixed potential.