The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 31, 2004

Filed:

Mar. 07, 2003
Applicant:
Inventors:

Kavita Nair, Eden Prairie, MN (US);

Ramesh Harjani, Minneapolis, MN (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03M 1/06 ;
U.S. Cl.
CPC ...
H03M 1/06 ;
Abstract

An analog to digital method and apparatus corrects non-linearity error and gain error in a multiple stage pipeline analog to digital converter over a plurality of clock cycles. Preferably, continuous correction, during each of the plurality of clock cycles, of at least portion of non-linearity error introduced by a digital to analog conversion is performed in a first stage of the multiple stage pipeline analog to digital converter with use of an averaging over time of a first stage digital residue signal provided by the remainder stages of the multiple stage pipeline analog to digital converter. Such correction is used to provide a non-linearity corrected digital signal. Correction, during each of the plurality of clock cycles, of at least a portion of a gain error introduced by one or more amplifiers in the multiple stage pipeline analog to digital converter is provided by averaging the non-linearity corrected digital signal over time.


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