The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 31, 2004

Filed:

Jun. 30, 2003
Applicant:
Inventors:

Jason Chung, Williston, VT (US);

Hongfei Wu, Colchester, VT (US);

Songtao Xu, South Burlington, VT (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03B 1/00 ;
U.S. Cl.
CPC ...
H03B 1/00 ;
Abstract

In order to reduce slew rate and minimize delay skew, the invention adds a pull-down booster circuit connected to the gate of the driving transistor and/or a pull-up booster circuit connected the gate of the driving transistor. The pull-down booster circuit is adapted to dynamically pull-down the voltage at the gate of the driving transistor when the voltage level at the input to the logical enable device changes from a first voltage (e.g., a logical “0”) to a second voltage (e.g., a logical “1”). The pull-up booster circuit is adapted to dynamically pull-up the voltage at the gate of the driving transistor when the voltage level at the input to the logical enable device changes from the second voltage to the first voltage.


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