Glitch free clock multiplexing circuit with asynchronous switch control and minimum switch over time

Abstract

A symmetric glitch free clock multiplexing circuit allows the input clock to a digital or analog processing unit to be switched from one frequency to the other at any moment during the operation, assuming the respective clocks themselves are stable. There exist no restrictions on the clocks or the switch control signal to be synchronous in any fashion. This circuit guarantees a glitch free output and also prevents short cycling of the output clock. Since all the related clocks and switch control signal are asynchronous, this circuit further eliminates meta-stability problems. Its symmetrical architecture allows the circuit to function with the output clock being switched from slow clock to fast clock and vise versa. More importantly, the complete switch over only takes two cycles of the targeted clock in the best case once the active clock is turned off, when switching from slow to fast clock; and four target clock cycles in the worst case once the active clock is turned off, when switching from fast to slow clock.