The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 31, 2004
Filed:
Dec. 18, 2002
Ryoichi Kajiwara, Hitachi, JP;
Masahiro Koizumi, Hitachi, JP;
Masayoshi Shinoda, Komoro, JP;
Akihiko Narisawa, Kodaira, JP;
Asao Nishimura, Koganel, JP;
Toshiaki Morita, Hitachi, JP;
Kazuya Takahashi, Hitachinaka, JP;
Kazutoshi Itou, Hitachi, JP;
Hitachi, Ltd., Tokyo, JP;
Abstract
In a semiconductor device in which an LSI chip comprising electrodes with a 100 &mgr;m pitch or less and 50 or more pins is mounted directly on an organic substrate, a mounting structure and a manufacturing method thereof are provided excellent in the solder resistant reflow property, temperature cycle reliability and high temperature/high humidity reliability of the semiconductor device. Electrode Au bumps of the chip and an Au film at the uppermost surface of connection terminals of the substrate are directly flip-chip bonded by Au/Au metal bonding and the elongation of the bonded portion of the Au bump is 2 &mgr;m or more. The method of obtaining the bonded structure involves a process of supersonically bonding both of the bonding surfaces within 10 min after sputter cleaning, under the bonding conditions selected from room temperature on the side of the substrate, room temperature to 150° C. on the side of the chip, a bonding load of ½S×100 MPa to S×180 MPa (S: contact area between bump and chip), a loading mode increasing during bonding, and supersonic application time of 50 to 500 ms.