The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 31, 2004

Filed:

Apr. 09, 2003
Applicant:
Inventors:

Chih-Chao Yang, Beacon, NY (US);

Yun Wang, Hopewell Junction, NY (US);

Larry Clevenger, Hopewell Junction, NY (US);

Andrew Simon, Fishkill, NY (US);

Stephen Greco, Hopewell Junction, NY (US);

Kaushik Chanda, Poughkeepsie, NY (US);

Terry Spooner, Hopewell Junction, NY (US);

Andy Cowley, Wappingers Falls, NY (US);

Sunfei Fang, Hopewell Junction, NY (US);

Assignee:

Other;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/144 ;
U.S. Cl.
CPC ...
H01L 2/144 ;
Abstract

A method of fabricating a semiconductor device having a dielectric structure on which an interconnect structure is optionally patterned using lithographic and etching techniques, within a single deposition chamber, is provided. The dielectric structure may optionally be covered by diffusion barrier materials prior to a sputter etching process. This sputter etching process is used to remove the native oxide on an underneath metal conductor surface and includes a directional gaseous bombardment with simultaneous deposition of metal neutral. Diffusion barrier materials may also be deposited into the pattern.


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