The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 31, 2004
Filed:
Apr. 12, 2002
Applicant:
Inventors:
Vladislav Vashchenko, Palo Alto, CA (US);
Ann Concannon, San Jose, CA (US);
Peter J. Hopper, San Jose, CA (US);
Marcel ter Beek, Pleasanton, CA (US);
Assignee:
National Semiconductor Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/18248 ;
U.S. Cl.
CPC ...
H01L 2/18248 ;
Abstract
In a Bi-CMOS ESD protection device, dual voltage capabilities are achieved by providing two laterally spaced p-regions in a n-material and defining a n+ region and a p+ region in each of the p-regions to define I-V characteristics that are similar to those defined by a SCR device in a positive direction, but, in this case, having those characteristics in both directions. The device may be asymmetrical to accommodate different voltage amplitudes in the positive and negative directions.