The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 24, 2004
Filed:
Feb. 19, 2003
Perry H. Pelley, Austin, TX (US);
John M. Burgan, North Palm Beach, FL (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
A memory ( ) has a memory array ( ), a charge pump ( ), a voltage regulator ( ), a refresh control circuit ( ), and a refresh counter ( ). The charge pump ( ) provides a substrate bias to the memory array ( ). The voltage regulator ( ) provides a pump enable signal for maintaining a voltage level of the substrate bias within upper and lower limits. The refresh control circuit ( ) controls refresh operations. The refresh counter ( ) is coupled to receive the pump enable signal, and in response, provides a refresh timing signal to the refresh control circuit ( ) to control a refresh rate of the memory array ( ). A programmable fuse circuit ( ) is provided to program the refresh rate using the counter ( ). The programmable fuse circuit ( ) may be programmed during wafer probe testing or board level burn-in. A built-in self test (BIST) circuit ( ) may be included to facilitate testing.