The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 24, 2004
Filed:
Apr. 18, 2002
Osamu Uno, Kasugai, JP;
Fujitsu Limited, Kawasaki, JP;
Abstract
In an input/output buffer circuit to which input signal voltage VBUS higher than power source voltage VDD is possibly inputted to an input/output terminal BUS, a gate terminal G is controlled by a signal in-phase to a input/output mode switching signal CNT outputted from a buffer circuit , and the power source voltage VDD is applied when it is an input mode. When the input signal voltage VBUS is lower than voltage obtained by applying threshold voltage Vthp of PMOS transistor to the power source voltage VDD (VBUS<VDD+Vthp), voltage obtained by subtracting threshold voltage Vthn of NMOS transistor from the power source voltage VDD is applied to a gate terminal G (VG =VDD−Vthn). On condition that Vthn>Vthp, a PMOS transistor P gets conductive, whereby the power source voltage VDD is applied to a gate terminal G and PMOS transistor P is turned off. Thereby, an unnecessary current path is not formed. There is thus provided an input/output buffer circuit wherein unnecessary current does not flow in the input/output terminal BUS.