The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 24, 2004
Filed:
Feb. 13, 2002
Shuji Yoshida, Kawasaki, JP;
Daisuke Miura, Kawasaki, JP;
Toshio Arakawa, Kawasaki, JP;
Mitsuaki Nagasaka, Kawasaki, JP;
Kenji Yoshida, Kawasaki, JP;
Hiroyuki Honda, Kawasaki, JP;
Kenji Kobayashi, Nagoya, JP;
Masayuki Okamoto, Kawasaki, JP;
Fujitsu Limited, Kawasaki, JP;
Abstract
Each binary carry logic circuit of half adder circuits other than that for the least significant digit comprises a transfer gate turned on when an input bit A is active and receiving a carry-in bit *C at its data input, and a transistor , turned on when the input bit A is inactive, connected between a power supply potential VDD and the data output of the transfer gate a signal on which is a carry-out bit *C . Transfer gates to of binary carry logic circuits other than that for the least significant digit are connected in chain, and are simultaneously on/off controlled by input bits A to A , letting the carry-in bit *C from the least significant digit propagate through the transfer gate chain at a high speed.