The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 24, 2004

Filed:

Sep. 27, 2002
Applicant:
Inventors:

Donald E. Steiss, Richardson, TX (US);

Clive Bittlestone, Lucas, TX (US);

Peter Cumming, La Gaude, FR;

Christopher Barr, Plano, TX (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 1/9173 ; H03K 1/900 ; H03K 3/289 ;
U.S. Cl.
CPC ...
H03K 1/9173 ; H03K 1/900 ; H03K 3/289 ;
Abstract

A flip flop ( ) comprising a master stage ( ) comprising a first plurality of transistors ( ), wherein each of the first plurality of transistors comprises a selective conductive path between a source and drain. The flip flop also comprises a slave stage ( ) comprising a second plurality of transistors ( ), wherein each of the second plurality of transistors comprises a selective conductive path between a source and drain. For the flip flop, in a low power mode the flip flop is operable to receive a first voltage (V ) coupled to the selective conductive path for each of the first plurality of transistors. Also in the low power mode, the flip flop is operable to receive a second voltage (V ) coupled to the selective conductive path for each of the second plurality of transistors. Lastly, the second voltage is greater than the first voltage in the low power mode.


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