The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 24, 2004
Filed:
Dec. 16, 2002
Frank Athari, Oceanside, CA (US);
Ron Brown, Riverside, CA (US);
Jonathan Adams, Rancho Palos Verdes, CA (US);
International Rectifer Corporation, El Segundo, CA (US);
Abstract
An integrated circuit for a continuous conduction mode (CCM) power factor corrected boost converter circuit, the boost converter circuit including a rectifier connectable to an ac input and having a rectified dc output provided across a dc bus; an inductor having first and second terminals connected in one leg of the dc bus, a first terminal of the inductor coupled to the output of said rectifier; a boost rectifier diode having a first terminal coupled to the second terminal of the inductor and having a second terminal; and a storage capacitor connected to the second terminal of the diode; the integrated circuit comprising a control circuit and a switch controlled by the control circuit, the integrated circuit comprising a housing enclosing the control circuit and switch, the integrated circuit having a power terminal, a ground terminal, a first control input terminal for coupling to an output of the converter circuit, and a second control input terminal for coupling to a sensor for sensing current in the de bus and further having an output terminal connected to the switch for coupling to the second terminal of the inductor, wherein the control circuit comprises a one cycle control circuit having an integrator reset by a clock signal for each cycle of the clock signal, the integrator receiving as an input a signal provided on said first control input terminal.