Spreading the power dissipation in mos transistors for improved esd protection

Abstract

An MOS transistor in the surface of a semiconductor substrate ( ) of a first conductivity type, which has a grid of isolations ( ) in the surface, each grid unit surrounding a rectangular substrate island ( ). Each island contains two parallel regions of the opposite conductivity type: one region ( ) is operable as the transistor drain and the other region ( ) is operable as the transistor drain, each region abutting the isolation. A transistor gate ( ) is between the parallel regions, completing the formation of a transistor. Electrical contacts ( ) are placed on the source region ( ) so that the spacing ( ) between each contact and the adjacent isolation is at least twice as large as the spacing ( ) between each contact and the gate. A plurality of these islands are interconnected to form a multi-finger MOS transistor. The source contact spacings are selected to increase the failure threshold current of the multi-finger MOS transistor by spreading the power dissipation and thus reducing the current localization, whereby the protection of the transistor against ESD pulses is improved.