The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 17, 2004

Filed:

Sep. 19, 2002
Applicant:
Inventor:

Kanji Natori, Fujimi-machi, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 1/604 ;
U.S. Cl.
CPC ...
G11C 1/604 ;
Abstract

A non-volatile semiconductor memory apparatus reduces the area occupied by circuits and thus the costs, and reduces the current consumption by providing a plurality of operating voltages by one charge pump circuit. A strong charge pump generates 5.0V and a power supply voltage of 8.0V. The power supply voltage is supplied to constant voltage circuits. The constant voltage circuits generate voltages according to the respective read, program and erase operation modes. These voltages are supplied to bit lines and control gate lines of the array block. In this manner, a plurality of operating voltages are obtained by using the power supply voltage from the charge pump to enable a read, program or erase operation for a non-volatile memory element of a twin memory cell. A plurality of operating voltages are generated by one strong charge pump, and thus the area occupied by circuits, the costs and the power consumption can be reduced.


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